Dyplo is a middleware solution to enable seamless integration of FPGA and software processes in applications. Dyplo links processes, executed on processor(s) and FPGA(s), with scalable software and hardware data streams embedded in the applied operating system. Dyplo managed processes, executed on FPGA fabric, share the same characteristics as software executed processes due to the extensive usage and support for partial reconfiguration, an advanced technology available in FPGAs. Using these properties, a full software-driven hardware development approach is made possible. This implies that the implementation of an application can be developed entirely in software while maintaining the software architecture, functions to be executed on FPGA fabric can be identified, isolated and replaced by FPGA functionality without compromising the program structure. This reduces to a high extend the low-level integration effort between FPGA and processor, which require development of bus interfaces, low level drivers and OS integration. With the partial reconfiguration FPGA fabric is reused in time, reducing the required FPGA size and as such reducing power requirements and FPGA cost.
Key Features and Benefits
- Design abstraction to system level.
- Dyplo Wizard confi guration tool to guarantee ease of use.
- High level of reuse capabilities over designs.
- Integrated support for high-level synthesis.
- Simple use of partial reconfi guration blocks in hardware.
- Software driven hardware development approach.
- Utilization of SOC devices to their maximum.